The present invention relates generally to integrated circuits, and, more particularly, to a system for processing bus transactions.
Advancements in semiconductor technology have led to an increase in the processing speed of central processing units (i.e., processors). In order to perform a task, processors communicate with peripheral devices by way of busses to read data from peripheral devices memories and store (write) data in the peripheral devices memories. It is essential that such stored data be accurate. Thus, modern day IC include circuits that support error correction techniques.
A known error correction technique is to generate and store protection code for stored data. This technique requires partitioning a memory into two partitions—one for the data and one for the protection code. However, the data and the protection code are accessed using the same channel (i.e., system bus) and hence, two memory access cycles are required to access the data and the corresponding protection code, which increases bus transaction processing time.
A known technique to overcome this increase in bus transaction processing time is to include two separate sets of connections (one for each partition) to access data and corresponding protection code from the memory. Thus, the data and the protection code are accessed in parallel from the two partitions. Although this technique increases the bus transaction processing speed, it requires modification of the system bus, and hence, is not a transparent solution for processing bus transactions. Further, for applications that do not require data protection, the partition dedicated to storing the protection code is unused, resulting in inefficient utilization of the memory space and bus width.
It would be advantageous to have a system and method that processes a bus transaction without requiring memory partitioning and system bus modification.